1. Field of the Invention
The present invention relates to a method for testing a semiconductor memory device, a test circuit for a semiconductor memory device, the semiconductor memory device and a semiconductor device. More particularly, the present invention relates to a method for testing whether or not data can be normally written into and read from a semiconductor memory device, a test circuit for a semiconductor memory device, a semiconductor memory device including the test circuit and a semiconductor device including a SOC (System On a Chip) (trademark) and the like. Specifically, in the SOC, a system including the test circuit, the semiconductor memory device, a CPU (central processing unit), a plurality of input/output means and the like, all of which are connected with each other via a bus, is built in one semiconductor chip.
2. Description of the Prior Art
In recent years, it is well known that information electronics include a SOC (System On a Chip) (trademark) in which a system includes a semiconductor memory device, a CPU (central processing unit), a plurality of input/output devices and the like, all of which are connected with each other via a bus, is built in one semiconductor chip. It is also well known that various methods for testing functions and performance of the above-described SOC have been developed. Particularly, a method for testing a semiconductor memory device mounted on the SOC is also well known. Such a method for testing a semiconductor memory device is disclosed, for example, in Japanese Patent Laid-Open No. Hei 7 (1995)-78495.
FIG. 1 depicts a block diagram showing a configuration example of a part of a semiconductor device to which a conventional method for testing a semiconductor memory device is applied.
The semiconductor device of this example includes: a PLLC (Phase Locked Loop Circuit) 1; an AGC (Address Generating Circuit) 2; a DGC (Data Generating Circuit) 3; a synchronous RAM macro 4; a DC (Data Comparator) 5; and switches 6 to 10. The switches 6 to 10 are all turned on in a normal operation of the semiconductor device of this example and are all turned off in testing. In testing, the PLLC 1 generates an internal clock ICK having a frequency four times that of an external clock ECK. In testing, the AGC 2 generates addresses of LSB two bits out of addresses A0 to An of n bits (n is a natural number) to be supplied to the RAM macro 4, in synchronization with the internal clock ICK.
In testing, the DGC 3 generates internal data IDT corresponding to external data EDT supplied from the outside, in synchronization with the internal clock ICK. In testing, based on a write enable signal WE supplied from the outside, the synchronous RAM macro 4 stores the internal data IDT supplied from the DGC 3 in storage regions corresponding to the addresses A2 to An of MSB (n−2) bits supplied from the outside and to the addresses A0 and A1 of LSB two bits supplied from the AGC 2, in synchronization with the internal clock ICK. In testing, the DC 5 compares output data read from the synchronous RAM macro 4 to an expected value pattern supplied from the outside.
As a result, the DC 5 determines whether or not the output data are strings of alternate 1s and 0s and its first data coincides with the expected value pattern and outputs a determination result TR.
The present inventor has recognized that storage capacity of the semiconductor memory device tends to increase year by year. Accordingly, a chip area is increased and miniaturization of a pattern is advanced. Thus, it has become more and more difficult to eliminate occurrence of defective memory cells incapable of writing and reading data in one semiconductor memory device.
In order to avoid the above-described problem, rescue of memory cells has been conventionally performed in the following manner. Specifically, extra rows and columns of memory cells (redundant memory cells) more than necessary storage capacity are provided in the semiconductor memory device and, in a probing test step of examining electrical characteristics and the like, a row including defective memory cells or a column including defective memory cells is replaced with the row of redundant memory cells or the column thereof. Thus, yield of the semiconductor memory device as a product has been improved.
In order to replace the above-described defect memory cells with the redundant memory cells, it is required to perform write and read of data for each of memory cells of the semiconductor memory device and determine whether the memory cell is a normal memory cell or a defective memory cell.
However, in the above-described conventional method for testing a semiconductor memory device, the DC 5 compares 4-bit output data read from the synchronous RAM macro 4 to a 4-bit expected value pattern supplied from the outside and determines whether or not the data and the pattern coincide with each other. Thus, there was a drawback that, even if the 4-bit output data is determined not to coincide with the 4-bit expected value pattern, it is impossible to determine which one of four memory cells corresponding to the 4-bit output data is not usable (fail). Consequently, the above-described conventional method for testing a semiconductor memory device cannot be used in the above-described probing test step.
On the above-described point, high-speed determination as described below is conceivable. Specifically, by supplying addresses one at a time from the outside in synchronization with the same clock as a high-speed internal clock ICK used in the semiconductor memory device, write and read of data is performed per bit to determine at high speed whether one corresponding memory cell is usable (pass) or not usable (fail).
However, in the above-described probing test step, it is required to perform arithmetic processing as to which one of memory cells of which one of semiconductor memory devices formed on a semiconductor wafer is a defective memory cell and to store the result thereof in storage means called a fail memory.
Therefore, the above-described arithmetic processing cannot keep up with such a high-speed test method. Thus, the method cannot be used in the foregoing probing test step.
The present invention was made in consideration of the above-described circumstances. It is an object of the present invention to provide a method for testing a semiconductor memory device, which is capable of obtaining read data corresponding to one external address one-on-one even if a high-speed internal clock obtained by multiplying a low-speed external clock is used, a test circuit for the semiconductor memory device, the semiconductor memory device and a semiconductor device.